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p reliminary w91031 calling line identif ier publication release date: august 2000 - 1 - revision a1 table of contents - general description ................................ ................................ ................................ .............................. 2 features and applications ................................ ................................ ................................ .................. 2 features ................................ ................................ ................................ ................................ ........................ 2 applications ................................ ................................ ................................ ................................ ................... 2 pin configuration ................................ ................................ ................................ ................................ .... 3 pin description ................................ ................................ ................................ ................................ .......... 3 system diagram ................................ ................................ ................................ ................................ ........ 5 block diagram ................................ ................................ ................................ ................................ ........... 6 functional description ................................ ................................ ................................ ........................ 6 ring detector ................................ ................................ ................................ ................................ ................. 6 input pre - processor ................................ ................................ ................................ ................................ ....... 8 dual tone alert signal detection ................................ ................................ ................................ .................... 8 fsk demodulation ................................ ................................ ................................ ................................ ....... 10 other fun ctions ................................ ................................ ................................ ................................ ........... 12 electrical characteristics ................................ ................................ ................................ .............. 14 absolute maximum ratings ................................ ................................ ................................ ......................... 14 recommended operating c onditions ................................ ................................ ................................ ........... 14 dc electrical characteristics ................................ ................................ ................................ ........................ 14 electrical characteristics - gain control op - amplifier ................................ ................................ .................. 16 ac electrical characteristics ................................ ................................ ................................ ........................ 16 ac timing characteristics ................................ ................................ ................................ ........................... 17 application information ................................ ................................ ................................ ..................... 22 application circuit ................................ ................................ ................................ ................................ ........ 22 application environment ................................ ................................ ................................ .............................. 23 the information described in this document is the exclusive intellectual property of winbond electronics corporation and shall not be reproduced without permission from winbond. winbond provides this document for reference purposes of w - based system design only. winbond assumes no responsibility for errors or omissions. all data and spe cifications are subject to change without notice.
p reliminary w9103 1 - 2 - general description the winbond caller identification device w91031, is a low power cmos integrated circuit used to receive physical layer signals transmitted according to bellcore and british telecom (bt) specifications. there are two types of caller identifications, the first type is on - hook calling with caller id message and the second type is call on waiting. the w91031 device provides all the features and functions of the caller identification specific ation for both these types, including fsk demodulation, tone alert signal detection and ring detection. the fsk demodulation function can demodulate bell 202 and ccitt v.23 frequency shift keying (fsk) with 1200 baud rate. the tone alert signal detect func tion can detect the dual tones of the bellcore cpe* tone alerting signal (cas) and the bt idle state and loop state tone alert signal. the line reversal for bt, ring burst for cca or ring signal for bellcore can be detected by the ring detector. there are two modes of fsk data output interface. the first mode is a data transfer activated by the device, whose clock and data change depending upon the changing frequency of the fsk analog signal input. the second mode allows a microcontroller to extract 8 - bit d ata from the device serially; the device notifies the micro - controller when 8 - bit data has been received. note: "cpe*" customer primises equipment features and applica tions features compatible with bellcore tr - nwt - 000030 & sr - tsv - 002476, british telecom (bt) sin227, u.k. cable communications association (cca) specification ring and line reversal detection bellcore cpe alerting signal (cas) and bt idle state and loop state tone alerting signal detection use dual tone alerting signal detector bell 2 02 and ccitt v.23 fsk demodulation with 1200 baud rate use 3.579545 mhz crystal or ceramic resonator low power cmos technology with sleep mode high input sensitivity variable gain input amplifier fsk carry detect output two modes for 3 - wire fsk data interface packaged in 24 - pin 0.6 inch (600 mil) plastic dip and 24 - pin 0.3 inch (300 mil) plastic sop applications bellcore calling identity delivery (cid), and bt calling line identity presentation (clip), cca clip systems feature phones ph one set adjunct boxes fax and answering machines data base telephone system and computer telephony integration (cti) systems
p reliminary w91031 publication release date: august 2000 - 3 - revision a1 pin configuration v algrc algr algo intn fcdn fdrn data dclk fske sleep/reset test2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 inp inn gcfb vref test1 rngdi rngrc rngon mode osci osco v w91031 dd ss top view pin description pin name type description 1 inp i non - inverting input of the gain con trol op - amp. 2 inn i inverting input of the gain control op - amp. 3 gcfb o op - amp feed - back gain control signal. select the input gain by connecting this pin and the inn pin with a feed - back resistor. it is recommended that the op - amp be set to unity gain . 4 vref o reference voltage. nominally, v dd /2 is used to bias the input of the gain control op - amp. 5 test1 i test pin, must be connected to v dd for normal operation. 6 rngdi i ring detect input (schmitt trigger input). used for ring detection and line reversal detection. must maintain a voltage between v dd and v ss . 7 rngrc o ring rc (open drain output and schmitt trigger input). used to set the time interval from the end of rngdi pin to the inactive condition of the rngon pin. an external resistor mus t connected to v dd and a capacitor connected to v ss , the time interval is the rc time constant. 8 rngon o ring detection output (low active). indicates the detection of line reversal and/or ringing. 9 mode i fsk data interface mode select. sets the fsk d ata output interface in mode 0 when low, or in mode 1 when high. 10 osci i oscillator input. a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and the osco pin. may be driven by an external clock source.
p reliminary w9103 1 - 4 - pin descriptions, continued pin name type description 11 osco o oscillator output. a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and the osci pin. should left open or to drive another clocked device when an external clock is connected to the osci pin. 12 v ss i power supply ground. 13 test2 i test pin. must be connected to v ss for normal operation. 14 sleep/ reset i reset or sleep input (schmitt input). when high the device will be reseted and enter a low power state by disabling the ga in control op - amp, the oscillator and other internal circuits. the function of rngdi, rngrc and the rngon pins are not affected when the device is in a sleep condition. this pin must be set low for normal operation. the device must reseted by micro control ler or by external rc pulse after power on. 15 fske i fsk enable. must be set high when for fsk demodulation. should be set low to disable the fsk demodulator and enable the dual tone alert signal detector when a dual tone alert signal is expected. 16 dc lk i, o data clock for the fsk interface. in the fsk data output interface mode 0 (mode pin low), this pin is an output with a changing fsk frequency. in the fsk interface mode 1, this pin is an input. 17 data o data signal for the fsk interface. serial d ata output according to the fsk frequency input in fsk data output interface mode 0 (mode pin low). data is shifted out on the rising edge of dclk in fsk data output interface mode 1. both logic 1 for mark and logic 0 for space. 18 fdrn o data ready of th e fsk interface (low active). in fsk interface mode 0 (mode pin low), this pin identifies the 8 - bit data boundary on the serial output string. in fsk interface mode 1, this pin is used to notify the micro - controller to extract the 8 - bit data (ie. 8 - bit dat a has been ready internally). 19 fcdn o fsk carrier detect (low active). when low, it indicates the fsk signal has been detected. 20 intn o interrupt signal (open drain). it is used to interrupt the microcontroller when rngon or fdrn are low, or if algo is high. remains low until all three signals have become inactive. 21 algo o dual tone alert signal guard time detect output. when high, a guard time qualified for the dual tone alert signal has been detected. 22 algr o dual tone alert signal guard time resistor. also functions as a dual tone alert signal detect output without guard time. an external resistor must connected between this pin and algrc to implement guard time detection. 23 algrc i dual tone alert signal guard time rc (cmos output and inter nal voltage comparator input). an external resistor must be connected between this pin and algr and an external capacitor between this pin and v dd to implement guard time detection. 24 v dd i power supply input.
p reliminary w91031 publication release date: august 2000 - 5 - revision a1 system diagram the w91031 device applicati ons include telephone systems which have caller id features and which can display the calling message on an lcd display. figure 5 shows the system diagram. it illustrates how to use the chip to connect between the tip/ring and the microcontroller in the te lephone system. the ring signal is detected by the w91031 device and then an interrupt sent to the microcontroller. the ring detected signal will also be directed to the ringer circuit. the data can be decoded by the microcontroller and displayed on the lc d display. the dtmf ack signal can also be generated by the dtmf generator if a call on waiting is performed. other functions are the same as the telephone set. micro controller handset speaker line interface winbond caller id (w91031) dtmf generator keypads lcd display ringer tip ring figure 5. system diagram for caller id application
p reliminary w9103 1 - 6 - block diagra m inp inn + - anti-alias filter fsk bandpass filter fsk demodulator fsk data output interface fsk carrier detector high tone bandpass filter low tone bandpass filter guard time circuit bias voltage generator to internal circuit oscillator & clock driver to internal circuit vref algrc intn fcdn fdrn data dclk sleep/ reset osci osco rngdi rngrc rngon vdd vss gcfb fske mode algr input pre-processor fsk demodulation circuit dual tone alert signal detection circuit ring detector high tone detector low tone detector interrupt generator power saving circuit algo figure 6. the block diagram of winbond caller id functional descripti on figure 6 is shown functional blocks of w91031. the device must operate with a 3.579545 mhz system clock and consists four major functions and decribed as follo ws: ring detector the application circuit in figure 7 - 1 illustrates the relationship between the rngdi, rngrc and rngon signals. the three pin combination is used to detect an increase of the rngdi voltage from ground to a level above the schmitt trigger h igh going threshold voltage v t+ .
p reliminary w91031 publication release date: august 2000 - 7 - revision a1 tip/a r1 = 470k c1 = 0.1uf ring/b c1 = 0.1uf c3 = 0.22uf r5=150k r2 = 470k r3 = 200k r4 = 300k rngdi w91031 rngr c rngon allowance minimal ring voltage (peak to peak) is: vpp (max ring) = 2 (v t+(max) (r1 + r3 + r4) / r4 + 0.7) tolerance to noise between tip and ring and vss is: vpeak (max noise) = v t+(min) (r1 + r3 + r4) / r4 + 0.7 ti me constant is: t = r5 c3 ln [v / (v - v t+ )] v t+(min) <= v t+ <= v t+(max) r5 from 10k ohm to 500k ohm. c3 from 47 nf to 0.68 uf. dd dd v dd v dd figure 7 - 1. application circuit of the ring detecter the rc time constant of the rngrc pin is used to delay the output pulse of the rngon pin for a low going edge on rngdi. this edge goes from above the v t+ voltage to the schmitt trigger low going threshold voltage v t - . the rc time constant must be greater than the maximum period of the ring signal, to ensure a minimum rngon low interval and to filter the ring signal to get an envelope output. the diode bridge shown in figure 7 - 1 works for both single ended ring signal and balanced ringing. r1 and r2 are used to set the maximum loading and must be of equal value to achieve balanced loading at both the tip and ring line. r1, r3 and r4 form a resi stor divider to supply a reduced voltage to the rngdi input. the attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground.
p reliminary w9103 1 - 8 - input pre - processor the input signal is processed by an in put pre - processor, which is added to the offset voltage to adjust the input amplitude and to filter out unwanted frequencies. the gain control op - amp is used to bias the input voltage with the vref signal voltage. the voltage of vref pin is v dd /2 typically , this pin must connected a 0.1 m f capacitor to v ss . it is also used to select the input gain by connecting a feedback resistor between this pin and the inn pin. figure 7 - 2 shows the necessary connections with the tip/ring line inputs. in a single - ended co nfiguration, the gain control op - amp is connected as shown in figure 7 - 3. inp inn + - gcfb r1 c1 c2 r2 r4 r3 r5 vref tip ring w91031 differential input amplifier c1 = c2 r1 = r2 r3 = (r4 r5) / (r4 +r5) voltage gain av = r5 / r1 input impedan ce zin = 2 r1 2 + (1 / wc) 2 0.1 uf figure 7 - 2 differential input gain control circuit c r1 r2 input + - inp inn gcfb vref voltage gain a v = r2 / r1 w91031 0.1 uf figure 7 - 3 single - ended input gain control circuit dual tone alert signal detection the dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. the dual tone alert signal detection circuit is enabled when the fske signal is low. it requires an enable time to enable the dual t one alert signal detector when fske goes from high to low. the algr is the output of the dual tone detector and when high indicates that the high tone and low tone alert signals have been detected. the guard time improves detection performance by rejecting detected signals with insufficient duration and by masking momentary detection dropout. figure 7 - 4 shows the relationship between the algr, algrc and algo pins and figure 7 - 5 shows the guard time waveform of the same pins. the total recognition time is t r ec = t dp + t gp , where t dp is the tone present detect time and t gp is the tone present guard time. the tone present guard time is the rc time constant with the capacitor discharging from v ss to v dd (the algrc pin discharges from v ss to v dd through a resisto r). the capacitor will discharge rapidly via a discharge switch after algo returns high. the total absent time is t abs = t da + t ga , where t da is the tone absent detect time and t ga is the tone absent guard time. the tone absent guard time is the rc time co nstant with the capacitor charging from v dd to v ss (the algrc pin charges from v dd to v ss through a resistor). the capacitor will charge rapidly via a charge switch after algo returns low. to obtain unequal present and absent guard times, a diode can be co nnected as shown in figure 7 - 6, to give the unequal resistance required during capacitor charging and discharging.
p reliminary w91031 publication release date: august 2000 - 9 - revision a1 dual tone detected v cpth - + comparator w91031 algrc algr algo vdd vdd r c discharge switch charge switch capacitor charge/discharge control circuit figure 7 - 4. guard time circuit of dual tone alert signal detection algr algrc algo discharge switch charge switch tip/ring on on on alerting signal v cpth v cpth t dp t gp t rec t da t ga t abs figure 7 - 5. guard tim e waveform of algr, algrc and algo pins
p reliminary w9103 1 - 10 - (a) t gp > t ga t gp dd = r1 c ln [v dd cpth / (v - v )] t ga = r p c ln [(v dd - v d (r p / r2)) / (v cp th - v d (r p / r2))] r p = r1 r2 / (r1 + r2) v d = diode forward voltage r1 r2 c algrc alr w91031 r1 r2 c algrc alr w91031 (b) t gp > t ga t gp dd = r1 c ln [v dd cpth / (v - v )] t ga = r p c ln [(v dd - v d (r p / r2)) / (v - v cpth - v d (r p / r2))] r p = r1 r2 / (r1 + r2) v d = diode forward voltage dd v dd v dd figure 7 - 6. guard time circuits with unequal present and absent time fsk demodulation the fsk demodulation circuit is enabled when the fske signal is high. an enable time is required t o enable the fsk demodulator circuitry after the fske signal goes from low to high. fsk carrier detector the fsk carrier detector provides an indication of the presence of a signal within the fsk frequency band. if the output amplitude of the fsk bandpass filter is of sufficient magnitude and holds for 8 ms, the fsk carrier detect output signal fcdn goes low. fcdn will be released if the fsk bandpass filter output amplitude is of insufficient magnitude for greater than 8 ms. the 8 ms hysteresis of the fsk c arrier detector is to allow for momentary signal drop out after fcdn has been activated. when fcdn is inactive, the output of the fsk demodulator is ignored by the fsk data output interface. in mode 0 of the 3 - wire fsk data output interface, dclk data and fdrn are all high and no clock and no data is driven. in mode 1, the internal shift registers are not updated, and fdrn is inactive (high state). the data is undefined if dclk is clocked. 3 - wire fsk interface the 3 - wire interface, dclk, data and fdrn pins, form the data interface of the fsk demodulation. the dclk pin is the data clock which is either generated by the w91031 or by an external device. the data pin is the serial data pin that outputs data to external devices. the fdrn pin is the data ready sig nal, also an output from the w91031 to external devices. there are two modes of this 3 - wire interface that can be selected. mode 0, where the data transfer is initiated by the w91031 device, or mode 1, where the data transfer is initiated by an external mi crocontroller.
p reliminary w91031 publication release date: august 2000 - 11 - revision a1 mode 0 (mode = low): the w91031 processes the fsk signal and outputs signals on the dclk, data and fdrn pins. figure 7 - 7 shows the timing diagram of the 3 - wire signals and the input of the fsk signal in mode 0. for each received stop and s tart bit sequence, the device outputs a fixed frequency clock string of 8 pulses on the dclk pin. each clock rising edge occurs in the middle of each data bit. dclk is not generated for the stop and start bits. the dclk pin is used as a clock driving signa l for a serial to parallel shift register or for a serial data input for a microcontroller. after the 8 - bit data has been shifted out by the device, the fdrn pin will supply a low pulse to inform the microcontroller to process the 8 - bit data. tip/ring 1* 1 0 b0 b1 b2 start b3 b4 b5 b6 b7 1* 0 b0 b1 b2 b3 b4 b5 b6 b7 1 1 0 b0 stop start stop start data b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 start stop start stop start t idd dclk fdrn 1/f dclk0 t crd t rl 1st byte data 2nd byte data 1st byte data 2nd byte data * mark bit or redundant stop bit(s), will be omitted. figure 7 - 7. serial data interface timing of fsk demodulation in mode 0 mode 1 (mode = high): the w91031 processes the fsk signal and sets the fdrn pin low to denote the 8 - bit boundary and to indicate to the microcontroller that new data has been transmitted. fdrn will return high on the first rising edge of dclk. fdrn is low for half of a nominal bit time (1/2400 sec) if dclk is not driven high. dclk is used to shift 8 - bit data out (lsb shift first) on the rising edge. after the last bit (msb) ha s been read, additional clock pulses on dclk are ignored. figure 7 - 8 shows the timing diagram of the 3 - wire signals and the input of the fsk signal in mode 1.
p reliminary w9103 1 - 12 - demodulated internal bit stream start 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 stop stop start data b0 b1 b2 b3 b4 b5 b6 b7 dclk fdrn 1/f dclk1 b7 b6 b5 1 b0 b0 b7 b6 t dds t ddh nth byte data (n + 1)th byte data (n - 1)th byte data nth byte data t rl note 2 note 1 1. fdrn cleared to high by dclk. 2. fdrn not cleared, low for maximum time (1/2 bit width). notes: figure 7 - 8. serial data interface timing of fsk demodulation in mode 1 oth er functions interrupt the interrupt intn is an open drain output and is used to interrupt the microcontroller. either rngon low, fdrn low or algo high will set intn low and will remain low until all of these three pins return to an inactive state. the mic rocontroller must read these pins to know what kind of interrupt occurred and to make the correct interrupt response. when the system is powered on, there is no charge on the capacitors. the voltage on the rngrc pin is low and rngon will be low. also the v oltage on the algrc pin is high and algo will be high if the sleep pin is low. this will cause an interrupt upon power up which will not be cleared until both capacitors are charged. the microcontroller should therefore ignore the interrupt from these sour ce until the capacitors are charged up. the microcontroller can examine the rngon and algo pins and wait until these signals are inactive during a power on interrupt. it is possible to clear the algo pin and its interrupt quickly by setting the sleep pin h igh. in the sleep mode, the algo pin is forced low and the charge switch in figure 7 - 4 will turn on, forcing the capacitor to charge up rapidly. sleep mode the w91031 can go into a sleep mode by setting sleep high, resulting in reduced power consumption. i n this mode, the gain control op - amp, oscillator and all internal circuits, except the ring detector are disabled. the rngdi, rngrc and rngon pins are not affected, so the device can still react to call arrival indicators and activate an interrupt to wake up the microcontroller. the sleep mode can be disabled by the microcontroller.
p reliminary w91031 publication release date: august 2000 - 13 - revision a1 crystal oscillator the operation frequency of the w91031 is 3.579545 mhz. crystal oscillators, ceramic resonators or other clock sources can be used. a crystal oscillator or ce ramic resonator can be directly connected to the osci and osco pins without the need for external components. if other clock sources are used, the osci pin should be driven by a clock source and the osco pin used to drive other external clocked devices, or left open. figure 7 - 9 shows some applications. the crystal specification is as follows: frequency: 3.579545 mhz frequency tolerance: +/ - 0.1 % ( - 40 c to +85 c) resonance mode: parallel load capacitance: 18 pf maximum series resistance: 150 w maximu m drive level (mv): 2 mv (a) with crystal osscillator or ceramic (b) with other clock osci osco 3.579545 mhz oscillator osco osci osco osci osco w91031 w91031 w91031 osci osco 3.579545 mhz w91031 figure 7 - 9. some application of clock driven circuit bias voltage generator the bias voltage generator provides a low impedance voltage source equal to v dd /2 and is used to bias the gain control op - amp. the voltage source is also used for internal circuits. a 0.1 m f capacitor should be placed between the vref pin and v ss to reduce noise.
p reliminary w9103 1 - 14 - electrical character istics absolute maximum ratings (voltage referenced to v ss pin) parameter symbol rating units supply voltage with respect to v ss v dd - 0.3 to 6 v voltage on any pin other than supplies (note 1) - 0.7 to v dd + 0.7 v current on any pin other than supplies 0 to 10 ma storage temperature t st - 65 to 150 c notes: 1. v dd +0.7 should not exceed the maximum rating of the supply voltage. 2. exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. recommended operating conditions (voltages referenced to v ss ) parameter symbol rating unit power supplies v dd 3.0 to 5.5 v clock frequency f osc 3.579545 mhz clock frequency tolerance d f c - 0.1 to +0.1 % operational temperature t op 0 to 75 c dc electrical characteristics (v dd - v ss = 3.0v. the dc electrical characteristics superse de the recommended operating conditions unless otherwise stated.) parameter condition sym. min. typ.* max. units test/ notes operating supply voltage 3.0 5.0 standby supply current i ddq 1 m a test 1 operating supply current v dd = 3.0v fske = fsk mode i dd1 1.0 1.4 ma test 2 v dd = 3.0v fske = alert mode i dd2 1.6 2.3 v dd = 5.0v fske = fsk mode i dd1 1.6 2.3 v dd = 5.0v fske = alert mode i dd2 2.5 3.6
p reliminary w91031 publication release date: august 2000 - 15 - revision a1 dc electrical characteristics, continued parameter condition sym. min. typ.* max. uni ts test/ notes schmitt input high threshold schmitt input low threshold rngdi, rngrc sleep vt+ vt - 0.48 v dd 0.28 v dd 0.68 v dd 0.48 v dd v v schmitt hysteresis vhys 0.2 v cmos input high voltage cmos input low voltage dclk, mode, fske v ih v il 0.7 v d d v ss v dd 0.3 v dd v output high source current rgnon, dclk, data, fdrn, fcdn, algo, algrc, algr i oh 0.5 ma note 1 output low sink current rgnon, dclk, data, fdrn, fcdn, algo, algrc, algr, intn i ol 0.5 ma note 2 rngrc i ol 2.5 ma note 2 input cu rrent 1 inp, inn, rngdi i in 1 1 m a note 3, 5 input current 2 sleep, dclk, mode, fske i i n 2 10 m a note 3, 5 output high - z current 1 rngrc i oz 1 1 m a note output high - z current 2 algrc i oz 2 5 m a 4, 5 output high - z current 3 intn i oz 3 10 m a refe rence output voltage vref v r ef 0.5 v dd - 4% 0.5 v dd +4% v note 6 reference output resistance vref rref 2 k w comparator threshold voltage algrc vcpth 0.5 v dd - 4% 0.5 v dd +4% v tests: 1: all input pins are v dd or v ss except for oscillator pins, no an alog inputs, output unloaded and sleep = v dd . 2: all input pins are v dd or v ss except for oscillator pins, no analog inputs, output unloaded, sleep = v ss and fske = v dd or fske = v ss . notes: " * " typical figure are at v dd = 5v and temperature = 25 c ar e design aids only, not guaranteed and not subject to production testing. 1. v oh = 0.9 v dd . 2. v ol = 0.1 v dd . 3. v in = v dd to v ss . 4. v out = v dd to v ss . 5. magnitude measurement, ignore signs. 6. output - no load.
p reliminary w9103 1 - 16 - electrical characteristics - gain control op - amplifier (electrical characteristics supersede the recommended operating conditions unless otherwise stated.) parameter sym. min. typ.* max. units test conditions input leakage current i in 1 ua v ss v in v dd input resistance r in 10 m w input offset voltage v os 25 mv power supply rejection ratio psrr 40 db 1 khz 0.1 vpp ripple on v dd maximum capacitive load (gcfb) c l 100 pf maximum resistive load (gcfb) r l 50 k w note: " * " typical figure are at v dd = 5v and temperature = 25 c a re design aids only, not guaranteed and not subject to production testing. ac electrical characteristics (ac electrical characteristics supersede the recommended operating conditions unless otherwise stated.) dual tone alert signal detection parameter sy m. min. typ. max. units notes low tone frequency f l 2130 hz high tone frequency f h 2750 hz frequency deviation acceptance 1.1 % 1 frequency deviation rejection 3.5 % 2 maximum input signal level 0.22 dbm a 3 input sensitivity per tone - 43 - 45 dbm 3, 4 reject signal level per tone - 54 dbm 3, 4 positive and negative twist b accept 7 db noise tolerance snr tone 20 db 3, 4, 5 notes: a. dbm = decibels with a reference power of 1 mw into 600 ohms, 0 dbm = 0.7746 vrms. b. twist = 2 0 log (f h amplitude / f l amplitude). 1: the range within which tones are accepted. 2: the range outside of which tones are rejected. 3: these characteristics are for v dd = 5v and temperature = 25 c. 4: both tones have the same amplitude. both tones are at the nominal frequencies. 5: band limited random noise 300 - 3400 hz. present only when the tone is present.
p reliminary w91031 publication release date: august 2000 - 17 - revision a1 fsk detection parameter symbol min. typ. max. units notes input frequency detection bell 202 mark (logic 1) bell 202 space (logic 0) ccitt v.23 mar k (logic 1) ccitt v.23 space (logic 0) fmark fspace fmark fspace 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 hz +/ - 1% +/ - 1% +/ - 1.5% +/ - 1.5% maximum input signal level - 5.78 dbm input sensitivity - 43 - 45 dbm 1, 2 transm ission rate 1188 1200 1212 baud input noise tolerance snrfsk 20 db 1, 2, 3 notes: 1: both mark and space have the same amplitude and are at the nominal frequencies. 2: these characteristics are fort v dd = 5v and temperature = 25 c. 3: band limited r andom noise 300 - 3400 hz. present only when the fsk signal is present. ac timing characteristics (ac timing characteristics supersede the recommended operating conditions unless otherwise stated.) system parameter symbol condition min. typ.* max. units n otes wake - up time t wake sleep 50 ms sleep - down time t slp osco 1 ms note: " * " typical figures are for v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to production testing. dual tone alert signal detection parameter symbol condition min. typ.* max. units notes alert detection enable time talte fske (low) 25 ms alert signal present detect time tdp algr 0.5 10 ms alert signal absent detect time tda 0.1 8 ms note: " * " typical figure are at v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to production testing. fsk detection parameter symbol condition min. typ.* max. units notes fsk detection enable time tfske fske (high) 25 ms input fsk to fcdn low delay tcp 25 ms
p reliminary w9103 1 - 18 - fsk detection, continued parameter symbol condition min. typ.* max. units notes input fsk to fcdn high delay tca fcdn 8 ms hysteresis 8 ms note: " * " typical figure are at v dd = 5v and temperature = 25 c are design aids only, n ot guaranteed and not subject to production testing. 3 - wire interface (mode 0) parameter symbol condition min. typ.* max. units notes rise time trr 200 ns 4 fall time trf fdrn 200 ns 4 low time trl 415 416 417 m s 2 rate data 1188 1200 1212 bps 1 input fsk to data delay tidd 1 5 ms rise time tr 200 ns 4 fall time tf dclk 200 ns 4 data to dclk delay tdcd data 6 416 m s 1, 2, 3 dclk to data delay tcdd 6 416 m s 1, 2, 3 frequency fdclk0 1201.6 1202.8 1204 hz 2 high time tch dclk 415 416 417 m s 2 low time tcl 415 416 417 m s 2 dclk to fdrn delay tcrd dclk, fdrn 415 416 417 m s 2 notes: " * " ttypical figure are for v dd = 5v and temperature = 25 c, are design aids only, not guaranteed and not subject to production testing. 1: fsk in put data rate at 1200 +/ - 12 baud. 2: osci frequency at 3.579545 mhz +/ - 0.1%. 3: function of signal condition. 4: 50 pf loading. 3 - wire interface (mode 1) parameter symbol condition min. typ.* max. units notes frequency fdclk1 1 mhz duty cycle dclk 3 0 70 % rise time tr1 20 ns dclk low set - up to fdrn tdds dclk, 500 ns dclk low hold time after fdrn tddh fdrn 500 ns note: " * " typical figure are at v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to production testing.
p reliminary w91031 publication release date: august 2000 - 19 - revision a1 sleep osco t wake t slp figure 8 - 1. wake up and sleep down timing tip/ring algr alerting signal t dp t da fske t alte alerting signal t dp t da note figure 8 - 2. alert detection enable and alert signal present and absent detect timing note: the minimal delay from fske low to algr high is t alte + t dp , if the alerting signal is present before t alte has elapsed. tip/ring fcdn analog fsk signal t cp t ca fske t fske analog fsk signal t cp t ca note figure 8 - 3. fsk detection enable and fsk carrier detect present and absent timing note: the minimal delay from fske high to fcdn high is t fske + t cp , if the analog fsk signal is present before t fske has elapsed.
p reliminary w9103 1 - 20 - data dclk v hm v ct v lm v hm v ct v lm t cl t ch t r t f t dcd t cdd t r t f v hm = 0.7 v , v ct = 0.5 v , v lm = 0.3 v dd dd dd figure 8 - 4. data and dclk mode 0 ouput timing fdrn t rf t rr t rl v hm v ct v lm v hm = 0.7 v , v ct = 0.5 v , v lm = 0.3 v dd dd dd figure 8 - 5. fdrn output timing tip/ring 1* 1 0 b0 b1 b2 start b3 b4 b5 b6 b7 1* 0 b0 b1 b2 b3 b4 b5 b6 b7 1 1 0 b0 stop start stop start data b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 start stop start stop start t idd dclk fdrn 1/f dclk0 t crd t rl 1st byte data 1st byte data 2nd byte data 2nd byte data * mark bit or redundant stop bit(s), will be omitted. figure 8 - 6. serial data interface timing of fsk demodulation in mode 0
p reliminary w91031 publication release date: august 2000 - 21 - revision a1 dclk t r1 v hm v lm v hm = 0.7 v , v dd lm = 0.3 v dd figure 8 - 7. dclk mode 1 input timing demodulated internal bit stream start 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 stop stop start data b0 b1 b2 b3 b4 b5 b6 b7 dclk fdrn 1/f dclk1 b7 b6 b5 1 b0 b0 b7 b6 t dds t ddh nth byte data (n + 1)th byte data (n - 1)th byte data nth byte data t rl note 2 note 1 1. fdrn cleared to high by dclk. 2. fdrn not cleared, low for maximum time (1/2 bit width). notes: figure 8 - 8. serial data interface timing of fsk demodulation in mode 1
p reliminary w9103 1 - 22 - application informat ion application circuit the application circuit of the w91031 in figure 9 - 1 shows the devi ce being used within a typical cpe system. note that only the circuit between the w91031 and the line interface is shown. the gain control op - amp is set to unity gain to allow the electrical characteristics to be met in this application circuit. it should also be noted that if a glitch with sufficient amplitude appears on the tip and ring interface, this will be detected as a ringing input by this circuit. inp inn gcfb vref test1 rngdi rngon mode osci osco vss rngrc vdd algrc algr algo intn fcdn fdrn data dclk fske sleep/ reset test2 34k 430k 22nf tip/a 430k 22nf ring/b 34k 464k 60k4 150k 0.22uf 200 k 300k 0.1uf 0.1uf r2 r1 53k6 w91031 fsk 3 - wire interface mode 0 selected. resistor must have 1% tolerance. resistor may have 5% tolerance. crystal is 3.579545mhz with 0.1% frequency tolerance. 470k 470k 0.1uf 10k r1, r2 must calculated acc ording to the formula of figure 7 - 6(a) for bellcore or bt application. must rest by microcontroller or by rc pulse. v dd v dd v dd v dd v dd v dd v dd v dd 0.1 uf figure 9 - 1. application circuit. another application circuit for the w9 1031, which provides common mode rejection of ringing circuit signals, is shown in figure 9 - 2. when the ac voltage between the tip and ring is greater than the zener diode breakdown voltage, the photo - coupler led will turn on, driving rngdi high and thus d etecting a ringing signal. note however in this case, a glitch on the tip and ring interface is not able to turn on the photo - coupler and therefore will not be detected as a ringing signal.
p reliminary w91031 publication release date: august 2000 - 23 - revision a1 inp inn gcfb vref test1 rngdi rngon mode osci osco vss rngrc vdd algrc algr algo intn fcdn fdrn data dclk fske sleep/ reset test2 34k 430k 22nf tip/a 430k 22nf ring/b 34k 464k 60k4 150k 0.22uf 200k 0.01uf 470k + - vz 0.1uf 0.33uf 12k 0.1uf r2 r1 v 53k6 w91031 fsk 3 - wire interface mode 0 selected. resistor must have 1% tolerance. resistor may have 5% tolerance. crystal is 3.579545mhz with 0.1% fr equency tolerance. r1, r2 must calculated according to the formula of figure 7 - 6(a) for bellcore or bt application. must reset by microcontroller or by rc pulse. dd v dd v dd v dd v dd v dd v dd v dd 0.1 uf figure 9 - 2. application circuit wit h improved common mode noise immunity application environment there are three major timing differences for caller id sequences, bellcore, bt and cca. figure 9 - 3 is the timing diagram for the bellcore on - hook data transmission and figure 9 - 4 is the timing d iagram for the bellcore off - hook data transmission. figure 9 - 5 is the timing diagram for the bt caller display service on - hook data transmission and figure 9 - 6 is the timing diagram for the bt caller display service off - hook data transmission. figure 9 - 7 i s the timing diagram for the cca caller display service for on - hook data transmission.
p reliminary w9103 1 - 24 - tip/ring rngon sleep fske fcdn fdrn dclk data 1st ring ch. seizure mark message 2nd ring note 1 note 2 ... ...101010... a b c d e f data ... note 4 note 3 note 5 intn ... ... det (c-mode) (m-mode or c-mode) figure 9 - 3. input and output timing of bellcore on - hook data transmission a = 2 sec typical b = 250 - 500 ms c = 250 ms d = 150 ms e = depends on data length max c + d + e = 2.9 to 3.7 sec f 3 200 ms notes : 1. the cpe designer may choose to wake up the w91031 only after the end of the rngon signal to conserve power for a battery operated cpe. the delay from rngon to slee p (and fske) is the reactive time of the microcontroller. 2. the cpe designer may choose to set fske to be always high while the cpe is on - hook, to ensure the fsk emodulator does not react to other in - band noise. 3. the microcontroller places the w91031 in a sleep condition after fcdn has become inactive. 4. the w91031 may not be woken up at this ring signal after the fsk data has been processed. 5. if the w91031 has been woken up at the 2nd ring, the microcontroller times out if fcdn is not activated and then puts the w91031 into a sleep condition.
p reliminary w91031 publication release date: august 2000 - 25 - revision a1 tip/ring sleep fske fcdn note 1 algo cpe unmutes handset and enables keypad g cas note 2 t rec t abs a b ack c cpe goes off-hook d e f mark message note 5 cpe sends cpe mutes handset & disables keypad note 3 fdrn dclk data ... data note 4 intn ... figure 9 - 4. input and output timing of bellcore off - hook data transmission a = 75 - 85 ms b = 0 - 100 ms c = 55 - 65 ms d = 0 - 500 ms e = 58 - 75 ms f = depends on data length g 5 0 ms notes: 1. in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off - hook and use battery power while on - hook. 2. the fske pin should be set low to enable the alert tone detector when the du al tone alert signal is expected. the cpe has the capability to disable the cas detection by setting fske always high during the on - hook state. 3. fske may be set high as soon as the cpe has finished sending the acknowledge signal ack. 4. fske should be set low when fcdn has become inactive. 5. for unsuccessful attempts where the end office does not send the fsk signal, the cpe should disable fske, unmute the handset and enable the keypad after this interval has elapsed.
p reliminary w9103 1 - 26 - a/b wires rngon sleep algo te dc load te ac load fske fcdn fdrn dclk data line reversal alert signal ch. seizure mark message ring t rec t abs 15 1 ms 20 5 ms a b c d e f g ... ... ...101010... data note 1 50 - 150 ms note 2 note 3 note 4 < 120 ua < 0.5 ma (optional) zss (refer to sin227) current wetting pulse (refer to sin227) intn ... ... a >= 100 ms b = 88 - 110 ms c >= 45 ms (up to 5 sec) d = 80 - 262 ms e = 45 - 75 ms f <= 2.5 sec (500 ms typical) g >= 200 ms figure 9 - 5. input and output timing of bt idle state (on - hook) data transmission notes: 1. sin227 specifies that the ac and dc loads should be applied at 20 5 ms after the end of the dual tone alert signal. 2. sin227 specifies that the ac and dc loads should be removed between 50 - 150 ms after the end of the fsk signal. the w91031 may also be placed in a sleep condition. 3. the fske pin should be set low to disable the fsk demodulator when fsk is not expected. the tone alerting signal speech and the dtmf tones are in the same frequency band as the fsk signal. 4. the w91031 may not be woken up at this ring signal after the fsk data has been processed.
p reliminary w91031 publication release date: august 2000 - 27 - revision a1 tip/ring sleep fske fcdn fdrn dclk data note 1 algo cpe unmutes handset and enables keypad g alert signal note 2 t rec t abs a b ack c cpe goes off-hook d e f mark message note 6 cpe sends cpe mutes handset & disables keypad note 4 ... data note 5 intn ... start point note 3 h figure 9 - 6. input and output timing of bt loop state (off - hook) data transmission a = 4 0 - 50 ms b = 80 - 85 ms c = 100 ms d = 65 - 75 ms e = 5 - 100 ms f = 45 - 75 ms g = depends on data length h 100 ms notes: 1. in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes of f - hook and use battery power while on - hook. 2. the fske pin should be set low to enable the alert tone detector when the dual tone alert signal is expected. 3. the exchange will have already disabled the speech path to the distant customer in both transmis sion directions. 4. the fske may be set high as soon as the cpe has finished sending the acknowledge signal ack. 5. fske should be set low when fcdn has become inactive. 6. in unsuccessful attempts where the exchange does not send the fsk signal, the cpe s hould disable fske, unmute the handset and enable the keypad after this interval.
p reliminary w9103 1 - 28 - a/b wires rngon sleep te dc load te ac load fske fcdn fdrn dclk data line reversal ring burst ch. seizure mark message first ring cycle a b c d e f ... ... ...101010... data note 2 note 3 note 4 intn ... ... a = 200 - 450 ms b >= 500 ms c = 80 - 262 ms d = 45 - 262 ms e <= 2.5 sec (500 ms typical) f >= 200 ms 250 - 400 ms 50 - 150 ms note 1 figure 9 - 7. input and output timing of cca caller display service data transmission notes: 1. the cpe designer may choose to set fske always high wh ile the the cpe is on - hook and the fsk signal is expected. 2. tw/p & e/312 specifies that the ac and dc loads should be applied between 250 - 400 ms after the end of the ring burst. 3. tw/p & e/312 specifies that the ac and dc loads should be removed between 50 - 150 ms after the end of the fsk signal. the w91031 may also be placed in a sleep condition. 4. the w91031 may not be woken up at the first ring cycle after the fsk data had been processed.
p reliminary w91031 publication release date: august 2000 - 29 - revision a1 headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice. headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice.

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